Referring to FIG. 1, a schematic of a dynamic random access memory (DRAM) cell 100 is shown. As shown, the memory cell comprises a transistor 110 and a trench capacitor 150. A first electrode 111 of the transistor is coupled to the bitline 125, and a second electrode 112 is coupled to the capacitor. A gate electrode 113 of the transistor is coupled to the wordline 126.
The trench capacitor, which is formed in the substrate, comprises first and second electrodes or plates 153 and 157 separated by a dielectric layer 155. The first plate 153 is coupled to the second electrode of the transistor. The first plate serves as a storage node for storing information.
A plurality of cells is arranged in rows and columns, connected by wordlines in the row direction and bitlines in the column direction. The second plate can be coupled to a constant voltage source 170 and serves as a common plate for the cells in the array.
A demand for higher integration resulted in a need to fabricate memory ICs with greater number of cells while reducing their surface area, creating difficulty in the manufacturing of such ICs. It is therefore desirable to provide memory cells which are conducive for higher density while keeping the size of the IC relatively small.